1. Field of the Invention
The present invention relates to a two-input, four-output high frequency switch circuit as a switch semiconductor integrated circuit formed on a semiconductor substrate. The invention also relates to a communications terminal, such as a portable telephone terminal, constructed using a high frequency switch circuit. The present invention is particularly suited to a two-input, four-output high frequency switch circuit of which low insertion loss and high isolation are required, and a communications terminal constructed using the same.
2. Description of the Related Art
Mobile communications business, including car telephones and portable telephone terminals, has been developing rapidly in recent years. Nowadays, a variety of mobile communications systems are in operation all over the world. In these mobile communications systems, many portable telephone terminals use semiconductor field-effect transistors in their signal processing sections.
For portable telephone terminals for which portability is particularly important, monolithic microwave ICs using GaAs field effect transistors have been vigorously developed as semiconductor integrated circuit devices that can simultaneously achieve smaller size, lower operating voltage, and lower power consumption. Among others, the development of high frequency switch circuits to be used in portable telephone terminals to switch high frequency signals has become a pressing need.
When using a field effect transistor as a switching device, the bias voltage to be applied to the gate terminal of the field effect transistor must be controlled. For example, the field effect transistor can be put in the ON state by applying to the gate terminal a gate bias sufficiently higher than the pinch off voltage and thereby putting the drain-source channel in a low impedance state in a controlled manner. Conversely, the field effect transistor can be put in the OFF state by applying to the gate terminal a gate bias sufficiently lower than the pinch off voltage and thereby putting the drain-source channel in a high impedance state in a controlled manner.
When using a GaAs field effect transistor alone as described above, there arises the problem that high isolation cannot be achieved, though the insertion loss is small. If high isolation is to be achieved with a field effect transistor alone, the gate width of the field effect transistor should be reduced. Reducing the gate width, however, results in increased ON resistance, and hence the problem of increased insertion loss. It is therefore difficult to achieve low insertion loss and high isolation at the same time.
In this way, when using a field effect transistor alone, it is difficult to achieve low insertion loss and high isolation at the same time. In view of this, a plurality of field effect transistors are used in combination to overcome this problem.
As an example of a switch circuit employing such a configuration, there is a single pole dual throw switch constructed using one series field effect transistor and one shunt field effect transistor in combination for each signal path. With this configuration, since a radio frequency signal leaking via a capacitive component of the series field effect transistor in the OFF state can be flown to ground through the shunt field effect transistor in the ON state, high isolation can be achieved.
On the other hand, in a digital portable telephone terminal using a time division multiple access communications scheme, a dual pole dual throw switch is used to switch between the attached antenna and an external antenna, i.e., a test antenna, and also switch between the transmitter and receiver sections built in the portable telephone terminal. A dual pole dual throw switch is a switch that has first and second input terminals and first and second output terminals, and that switches signals from the first and second input terminals to the first and second output terminals, respectively, or conversely to the second and first output terminals, respectively.
As an example of equipment using such a dual pole dual throw switch, a communications terminal will be described below.
FIG. 5 shows the RF section, i.e., the radio frequency signal processing section, of the communications terminal which uses the dual pole dual throw switch. This communications terminal is constructed to be able to switch connections between two antennas 1, 2 and transmitter and receiver sections 3, 4.
For this purpose, the dual pole dual throw switch 7 is provided with four signal terminals RF2, RF4, RF5, and RF6. A switch S3 is inserted, that is, connected in series, in a signal path connecting between the signal terminal RF2 and the signal terminal RF4. A switch S4 is inserted, that is, connected in series, in a signal path connecting between the signal terminal RF4 and the signal terminal RF5. A switch S5 is inserted, that is, connected in series, in a signal path connecting between the signal terminal RF5 and the signal terminal RF6. A switch S6 is inserted, that is, connected in series, in a signal path connecting between the signal terminal RF6 and the signal terminal RF2. The receiver section 4 is connected to the signal terminal RF2, and the transmitter section 3 is connected to the signal terminal RF5. The antenna 1 is connected to the signal terminal RF6, and the antenna 2 is connected to the signal terminal RF4.
Using the above configuration, signals to be input to the receiver section 4 can be input by switching between the two antennas 1 and 2. Likewise, output signals from the transmitter section 3 can be transmitted by switching between the two antennas 1 and 2.
However, today""s portable telephone terminals use two antennas, i.e., a whip antenna as a transmitting/receiving antenna and a built-in antenna as a receiving antenna, for diversity reception. Further, to inspect such portable telephone terminals at the factory, two test antennas, one corresponding to the whip antenna and the other to the built-in antenna, are used.
To serve the purpose, the high frequency switch circuit is provided with four signal terminals as antenna terminals connected to the first, second, third, and fourth antennas, respectively. The first antenna is the whip antenna. The second antenna is the built-in antenna. The third antenna is the test antenna corresponding to the first antenna. The fourth antenna is the test antenna corresponding to the second antenna. The antenna terminals connected to the third and fourth antennas are called the test terminals, which are connected to the test antennas at the time of factory testing but are left open during normal use.
Therefore, the high frequency switch circuit has three switching functions, one for switching between transmission and reception, another for switching between the first and second antennas and the third and fourth antennas, and the other for switching between the receiving antennas for diversity reception, and is constructed so that any switch path can be connected within the high frequency switch circuit.
As an example of equipment using such a high frequency switch circuit, a communications terminal will be described below.
FIG. 6 shows the RF section, i.e., the radio frequency signal processing section, of the communications terminal which uses the high frequency switch circuit. This communications terminal uses a two-input, four-output switch 8 as the high frequency switch circuit, instead of the dual pole dual throw switch 7 shown in FIG. 5. The two-input, four-output switch 8 differs from the dual pole dual throw switch 7 shown in FIG. 5 by the addition of two signal terminals RF1 and RF3. A switch S1 is inserted, that is, connected in series, in a signal path connecting between the signal terminal RF2 and the signal terminal RF1. A switch S2 is inserted, that is, connected in series, in a signal path connecting between the signal terminal RF2 and the signal terminal RF3. An antenna 5 is connected to the signal terminal RF1, while an antenna 6 is connected to the signal terminal RF3.
Here, the antenna 1 is a whip antenna, the antenna 2 is a test antenna corresponding to the whip antenna, the antenna 5 is a built-in antenna, and the antenna 6 is a test antenna corresponding to the built-in antenna.
Though the name xe2x80x9ctwo-input, four-output switchxe2x80x9d is used throughout this specification, this is for convenience only, and it will be understood that there are cases in which the input/output relations, that is, signal propagation directions, are reversed from what the name suggests.
FIG. 7 is a circuit diagram showing the detailed configuration of the two-input, four-output switch 8 shown in FIG. 6. In FIG. 7, reference characters FET1 to FET6 indicate series field effect transistors forming the switches S1 to S6, respectively. Reference character FET7 designates a shunt field effect transistor for connecting the signal terminal RF6 to ground GND which is a reference potential. Reference character FET8 denotes a shunt field effect transistor for connecting the signal terminal RF1 to the ground GND, the reference potential. The ON/OFF operations of the field effect transistors FET1 to FET8 are controlled by control bias voltages CTL1 to CTL8, respectively. The remainder of the configuration is the same as that described with reference to FIG. 6.
In the prior art, the field effect transistors FET7 and FET8 simply act to connect the respective signal terminals RF6 and RF1 to the ground GND, the reference potential. In other words, neither of the field effect transistors FET7, FET8 has a characteristic impedance to be matched to an external circuit.
Next, transmit and receive operations of the communications terminal shown in FIGS. 6 and 7 will be described. In the time division multiple access scheme, transmit and receive operations are not performed simultaneously. Therefore, in the time division multiple access scheme, the transmit and receive operations are performed in time division fashion in a controlled manner by switching the control bias voltages CTL1 to CTL8 between high and low. The operating states of the two-input, four-output switch 8 based on the control bias voltages CTL1 to CTL8 are shown in the form of a truth table in FIG. 8.
First, a description will be given of how the connection between the signal terminal RF1 and the signal terminal RF2 is turned on. In this case, the control bias voltages CTL1 to CTL8 are set to the voltage levels shown in the ON PORT xe2x80x9cRF2-RF1xe2x80x9d row in FIG. 8. As a result, the field effect transistors FET1 and FET7 are ON, and the field effect transistors FET2 to FET6 and FET8 are OFF. This puts the signal path between the signal terminal RF1 and the signal terminal RF2 in a low loss state, and the signal path between the signal terminal RF1 and the signal terminal RF2 is thus put in a state that can carry a radio frequency signal therethrough.
Next, a description will be given of how the connection between the signal terminal RF3 and the signal terminal RF2 is turned on. In this case, the control bias voltages CTL1 to CTL8 are set to the voltage levels shown in the ON PORT xe2x80x9cRF2-RF3xe2x80x9d row in FIG. 8. As a result, the field effect transistors FET2, FET7, and FET8 are ON, and the field effect transistors FET1 and FET3 to FET6 are OFF. This puts the signal path between the signal terminal RF3 and the signal terminal RF2 in a low loss state, and the signal path between the signal terminal RF3 and the signal terminal RF2 is thus put in a state that can carry a radio frequency signal therethrough.
Next, a description will be given of how the connection between the signal terminal RF6 and the signal terminal RF2 is turned on. In this case, the control bias voltages CTL1 to CTL8 are set to the voltage levels shown in the ON PORT xe2x80x9cRF2-RF6xe2x80x9d row in FIG. 8. As a result, the field effect transistors FET4, FET6, and FET8 are ON, and the field effect transistors FET1 to FET3, FET5, and FET7 are OFF. This puts the signal path between the signal terminal RF6 and the signal terminal RF2 in a low loss state, and the signal path between the signal terminal RF6 and the signal terminal RF2 is thus put in a state that can carry a radio frequency signal therethrough.
Next, a description will be given of how the connection between the signal terminal RF4 and the signal terminal RF2 is turned on. In this case, the control bias voltages CTL1 to CTL8 are set to the voltage levels shown in the ON PORT xe2x80x9cRF2-RF4xe2x80x9d row in FIG. 8. As a result, the field effect transistors FET3, FET5, FET7, and FET8 are ON, and the field effect transistors FET1, FET2, FET4, and FET6 are OFF. This puts the signal path between the signal terminal RF4 and the signal terminal RF2 in a low loss state, and the signal path between the signal terminal RF4 and the signal terminal RF2 is thus put in a state that can carry a radio frequency signal therethrough.
Next, a description will be given of how the connection between the signal terminal RF5 and the signal terminal RF6 is turned on. In this case, the control bias voltages CTL1 to CTL8 are set to the voltage levels shown in the ON PORT xe2x80x9cRF5-RF6xe2x80x9d row in FIG. 8. As a result, the field effect transistors FET3, FET5, and FET8 are ON, and the field effect transistors FET1, FET2, FET4, FET6, and FET7 are OFF. This puts the signal path between the signal terminal RF5 and the signal terminal RF6 in a low loss state, and the signal path between the signal terminal RF5 and the signal terminal RF6 is thus put in a state that can carry a radio frequency signal therethrough.
Next, a description will be given of how the connection between the signal terminal RF5 and the signal terminal RF4 is turned on. In this case, the control bias voltages CTL1 to CTL8 are set to the voltage levels shown in the ON PORT xe2x80x9cRF5-RF4xe2x80x9d row in FIG. 8. As a result, the field effect transistors FET4 and FET6 to FET8 are ON, and the field effect transistors FET1 to FET3 and FET5 are OFF. This puts the signal path between the signal terminal RF5 and the signal terminal RF4 in a low loss state, and the signal path between the signal terminal RF5 and the signal terminal RF4 is thus put in a state that can carry a radio frequency signal therethrough.
However, in the above prior art configuration, when switching is made to pass a signal through a particular path, paths at open ends are left unconnected with any paths. For example, in FIG. 7, when the path between the signal terminal RF1 and the signal terminal RF2 is turned on, the signal terminal RF3 and the signal terminal RF4 become open ends while on board the system, and standing waves are produced on the paths passing through the signal terminals RF3 and RF4.
The paths passing through the signal terminals RF3 and RF4, on which the standing waves are produced, are isolated from the signal path between the signal terminal RF1 and the signal terminal RF2 by turning off the field effect transistors FET2, FET3, etc. The field effect transistors FET2 and FET3 in the OFF state can be regarded as capacitors, and therefore, the signal path is regarded as being isolated by the capacitors from the paths on which the standing waves are produced. At this time, however, the capacitors for isolating them cannot completely eliminate the effects of the standing waves. The resulting problem is that insertion loss in the signal path abruptly increases at specific frequencies because of the effects of the standing waves, that is, the insertion loss is frequency dependent. In other words, the insertion loss exhibits in-band ripples.
FIG. 9 shows the measured results of the insertion loss in the prior art configuration. The frequency is plotted along the abscissa and the insertion loss along the ordinate. As can be seen from FIG. 9, the insertion loss abruptly increases at certain frequencies.
A configuration in which a shunt field effect transistor is connected to a dual pole dual throw switch is disclosed, for example, in Japanese Unexamined Patent Publication No. 9-55682. In a dual pole dual throw switch, there are no terminals left open. However, in a two-input, four-output switch, the four terminals which are not used for the signal path can become open ended.
An open ended terminal on a semiconductor substrate is connected to leads by bonding wire, and the semiconductor substrate, the bonding wire, and the leads constitute a semiconductor device. The leads are connected to wiring lines and other devices on the printed circuit board. With such elements connected to the open ended terminal, a resonant circuit is formed. The effect of this resonance manifests itself in the form of a standing wave at the open ended terminal, and this affects the signal coupled to the open ended terminal via a field effect transistor FET.
This is a significant difference between the dual pole dual throw switch and the two-input, four-output switch of the present invention.
An object of the present invention is to provide a high frequency switch circuit that can alleviate the problem of the frequency dependence of insertion loss, and also provide a communications terminal using the same.
To achieve the above object, the high frequency switch circuit of the present invention, which is used as a high frequency switch circuit in a portable telephone terminal, includes a switch for matching an open ended path to an external impedance. The communications terminal is constructed using this high frequency switch circuit. The high frequency switch circuit here refers to a two-input, four-output switch.
More specifically, a high frequency switch circuit according to a first invention comprises: first, second, third, fourth, fifth, and sixth signal terminals; a first switch inserted in a first signal path connecting between the first signal terminal and the second signal terminal; a second switch inserted in a second signal path connecting between the second signal terminal and the third signal terminal; a third switch inserted in a third signal path connecting between the second signal terminal and the fourth signal terminal; a fourth switch inserted in a fourth signal path connecting between the fourth signal terminal and the fifth signal terminal; a fifth switch inserted in a fifth signal path connecting between the fifth signal terminal and the sixth signal terminal; a sixth switch inserted in a sixth signal path connecting between the second signal terminal and the sixth signal terminal; a seventh switch for selecting whether the sixth signal terminal is to be connected to a reference potential or be left open; an eighth switch for selecting whether the first signal terminal is to be connected to the reference potential (GND) or be left open; a ninth switch for selecting whether the fourth signal terminal is to be connected to the reference potential (GND) or be left open; and a tenth switch for selecting whether the third signal terminal is to be connected to the reference potential (GND) or be left open.
In the above configuration, each of the seventh, eighth, ninth, and tenth switches, when ON, exhibits a characteristic impedance that satisfies a matching condition to the characteristic impedance of an associated one of first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively.
In the high frequency switch circuit of the first invention described above, the seventh, eighth, ninth, and tenth switches are provided to select whether the sixth, first, fourth, and third signal terminals, respectively, are to be connected to the reference potential or be left open, and each of the seventh, eighth, ninth, and tenth switches is designed so as to exhibit, when ON, a characteristic impedance that satisfies the matching condition to the characteristic impedance of an associated one of the first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively. According to this configuration, when the sixth, first, fourth, and third signal terminals, respectively, are not used for a signal path, the seventh, eighth, ninth, and tenth switches, respectively, are caused to conduct, thereby suppressing the effects of standing waves on the signal path and thus alleviating the problem of the frequency dependence of insertion loss.
A high frequency switch circuit according to a second invention comprises: first, second, third, fourth, fifth, and sixth signal terminals; a first field effect transistor circuit inserted in a first signal path connecting between the first signal terminal and the second signal terminal; a second field effect transistor circuit inserted in a second signal path connecting between the second signal terminal and the third signal terminal; a third field effect transistor circuit inserted in a third signal path connecting between the second signal terminal and the fourth signal terminal; a fourth field effect transistor circuit inserted in a fourth signal path connecting between the fourth signal terminal and the fifth signal terminal; a fifth field effect transistor circuit inserted in a fifth signal path connecting between the fifth signal terminal and the sixth signal terminal; a sixth field effect transistor circuit inserted in a sixth signal path connecting between the second signal terminal and the sixth signal terminal; a seventh field effect transistor circuit connected between the sixth signal terminal and a reference potential; an eighth field effect transistor circuit connected between the first signal terminal and the reference potential; a ninth field effect transistor circuit connected between the fourth signal terminal and the reference potential; a tenth field effect transistor circuit connected between the third signal terminal and the reference potential; and first to tenth control lines for applying first to tenth control bias voltages to the control terminals of the first to tenth field effect transistor circuits.
In the above configuration, each of the seventh, eighth, ninth, and tenth field effect transistor circuits, when ON, exhibits a characteristic impedance that satisfies a matching condition to the characteristic impedance of an associated one of first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively.
In the high frequency switch circuit of the second invention described above, the seventh, eighth, ninth, and tenth field effect transistor circuits are provided between the reference potential and the sixth, first, fourth, and third signal terminals, respectively, and each of the seventh, eighth, ninth, and tenth field effect transistor circuits is designed so as to exhibit, when ON, a characteristic impedance that satisfies the matching condition to the characteristic impedance of an associated one of the first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively. According to this configuration, when the sixth, first, fourth, and third signal terminals, respectively, are not used for a signal path, the seventh, eighth, ninth, and tenth field effect transistor circuits, respectively, are operated and caused to conduct, thereby suppressing the effects of standing waves on the signal path and thus alleviating the problem of the frequency dependence of insertion loss.
A high frequency switch circuit according to a third invention comprises: first, second, third, fourth, fifth, and sixth signal terminals; a first field effect transistor circuit inserted in a first signal path connecting between the first signal terminal and the second signal terminal; a second field effect transistor circuit inserted in a second signal path connecting between the second signal terminal and the third signal terminal; a third field effect transistor circuit inserted in a third signal path connecting between the second signal terminal and the fourth signal terminal; a fourth field effect transistor circuit inserted in a fourth signal path connecting between the fourth signal terminal and the fifth signal terminal; a fifth field effect transistor circuit inserted in a fifth signal path connecting between the fifth signal terminal and the sixth signal terminal; a sixth field effect transistor circuit inserted in a sixth signal path connecting between the second signal terminal and the sixth signal terminal; a series circuit consisting of a seventh field effect transistor circuit and a first resistor, and connected between the sixth signal terminal and a reference potential; a series circuit consisting of an eighth field effect transistor circuit and a second resistor, and connected between the first signal terminal and the reference potential; a series circuit consisting of a ninth field effect transistor circuit and a third resistor, and connected between the fourth signal terminal and the reference potential; a series circuit consisting of a tenth field effect transistor circuit and a fourth resistor, and connected between the third signal terminal and the reference potential; and first to tenth control lines for applying first to tenth control bias voltages to the control terminals of the first to tenth field effect transistor circuits.
In the above configuration, sum of an ON-state characteristic impedance of the seventh field effect transistor circuit and a resistance value of the first resistor satisfies a matching condition to the characteristic impedance of a first external circuit connected to the sixth signal terminal. At the same time, sum of an ON-state characteristic impedance of the eighth field effect transistor circuit and a resistance value of the second resistor satisfies a matching condition to the characteristic impedance of a second external circuit connected to the first signal terminal. At the same time, sum of an ON-state characteristic impedance of the ninth field effect transistor circuit and a resistance value of the third resistor satisfies a matching condition to the characteristic impedance of a third external circuit connected to the fourth signal terminal. And at the same time, sum of an ON-state characteristic impedance of the tenth field effect transistor circuit and a resistance value of the fourth resistor satisfies a matching condition to the characteristic impedance of a fourth external circuit connected to the third signal terminal.
In the high frequency switch circuit of the third invention described above, the series circuits formed by connecting the seventh, eighth, ninth, and tenth field effect transistors in series with the first, second, third, and fourth resistors, respectively, are provided between the reference potential and the sixth, first, fourth, and third signal terminals, respectively, and the characteristic impedances of the respective series circuits when the respective seventh, eighth, ninth, and tenth field effect transistors are ON are set so as to satisfy the matching conditions to the characteristic impedances of the first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively. According to this configuration, when the sixth, first, fourth, and third signal terminals, respectively, are not used for a signal path, the seventh, eighth, ninth, and tenth field effect transistor circuits, respectively, are operated and caused to conduct. This alleviates the problem of the frequency dependence of insertion loss. Furthermore, since the impedance is provided using a resistor, the ON-state impedance of each field effect transistor can be reduced. As a result, the seventh, eighth, ninth, and tenth field effect transistors can be reduced in size by forming their associated resistors on the same semiconductor substrate, and hence, the chip size can be reduced.
A communications terminal according to a fourth invention comprises: a high frequency switch circuit having first, second, third, fourth, fifth, and sixth signal terminals; first, second, third, and fourth antennas electrically connected to the first, third, fourth, and sixth signal terminals, respectively; a receiver section which is connected to the second signal terminal, and to which high frequency signals received at the first, second, third, and fourth antennas are input; and a transmitter section which is connected to the fifth signal terminal, and which outputs high frequency signals to the third and fourth antennas.
The above high frequency switch circuit comprises: a first switch inserted in a first signal path connecting between the first signal terminal and the second signal terminal; a second switch inserted in a second signal path connecting between the second signal terminal and the third signal terminal; a third switch inserted in a third signal path connecting between the second signal terminal and the fourth signal terminal; a fourth switch inserted in a fourth signal path connecting between the fourth signal terminal and the fifth signal terminal; a fifth switch inserted in a fifth signal path connecting between the fifth signal terminal and the sixth signal terminal; a sixth switch inserted in a sixth signal path connecting between the second signal terminal and the sixth signal terminal; a seventh switch for selecting whether the sixth signal terminal is to be connected to a reference potential or be left open; an eighth switch for selecting whether the first signal terminal is to be connected to the reference potential (GND) or be left open; a ninth switch for selecting whether the fourth signal terminal is to be connected to the reference potential (GND) or be left open; and a tenth switch for selecting whether the third signal terminal is to be connected to the reference potential (GND) or be left open.
In the above configuration, each of the seventh, eighth, ninth, and tenth switches, when ON, exhibits a characteristic impedance that satisfies a matching condition to the characteristic impedance of an associated one of first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively.
According to this configuration, the same advantageous effect as that achieved by the high frequency switch circuit of the first invention can be obtained.
A communications terminal according to a fifth invention comprises: a high frequency switch circuit having first, second, third, fourth, fifth, and sixth signal terminals; first, second, third, and fourth antennas electrically connected to the first, third, fourth, and sixth signal terminals, respectively; a receiver section which is connected to the second signal terminal, and to which high frequency signals received at the first, second, third, and fourth antennas are input; and a transmitter section which is connected to the fifth signal terminal, and which outputs high frequency signals to the third and fourth antennas.
The above high frequency switch circuit comprises: a first field effect transistor circuit inserted in a first signal path connecting between the first signal terminal and the second signal terminal; a second field effect transistor circuit inserted in a second signal path connecting between the second signal terminal and the third signal terminal; a third field effect transistor circuit inserted in a third signal path connecting between the second signal terminal and the fourth signal terminal; a fourth field effect transistor circuit inserted in a fourth signal path connecting between the fourth signal terminal and the fifth signal terminal; a fifth field effect transistor circuit inserted in a fifth signal path connecting between the fifth signal terminal and the sixth signal terminal; a sixth field effect transistor circuit inserted in a sixth signal path connecting between the second signal terminal and the sixth signal terminal; a seventh field effect transistor circuit connected between the sixth signal terminal and a reference potential; an eighth field effect transistor circuit connected between the first signal terminal and the reference potential; a ninth field effect transistor circuit connected between the fourth signal terminal and the reference potential; a tenth field effect transistor circuit connected between the third signal terminal and the reference potential; and first to tenth control lines for applying first to tenth control bias voltages to the control terminals of the first to tenth field effect transistor circuits.
In the above configuration, each of the seventh, eighth, ninth, and tenth field effect transistor circuits, when ON, exhibits a characteristic impedance that satisfies a matching condition to the characteristic impedance of an associated one of first, second, third, and fourth external circuits connected to the sixth, first, fourth, and third signal terminals, respectively.
According to this configuration, the same advantageous effect as that achieved by the high frequency switch circuit of the second invention can be obtained.
A communications terminal according to a sixth invention comprises: a high frequency switch circuit having first, second, third, fourth, fifth, and sixth signal terminals; first, second, third, and fourth antennas electrically connected to the first, third, fourth, and sixth signal terminals, respectively; a receiver section which is connected to the second signal terminal, and to which high frequency signals received at the first, second, third, and fourth antennas are input; and a transmitter section which is connected to the fifth signal terminal, and which outputs high frequency signals to the third and fourth antennas.
The above high frequency switch circuit comprises: a first field effect transistor circuit inserted in a first signal path connecting between the first signal terminal and the second signal terminal; a second field effect transistor circuit inserted in a second signal path connecting between the second signal terminal and the third signal terminal; a third field effect transistor circuit inserted in a third signal path connecting between the second signal terminal and the fourth signal terminal; a fourth field effect transistor circuit inserted in a fourth signal path connecting between the fourth signal terminal and the fifth signal terminal; a fifth field effect transistor circuit inserted in a fifth signal path connecting between the fifth signal terminal and the sixth signal terminal; a sixth field effect transistor circuit inserted in a sixth signal path connecting between the second signal terminal and the sixth signal terminal; a series circuit consisting of a seventh field effect transistor circuit and a first resistor, and connected between the sixth signal terminal and a reference potential; a series circuit consisting of an eighth field effect transistor circuit and a second resistor, and connected between the first signal terminal and the reference potential; a series circuit consisting of a ninth field effect transistor circuit and a third resistor, and connected between the fourth signal terminal and the reference potential; a series circuit consisting of a tenth field effect transistor circuit and a fourth resistor, and connected between the third signal terminal and the reference potential; and first to tenth control lines for applying first to tenth control bias voltages to the control terminals of the first to tenth field effect transistor circuits.
In the above configuration, sum of an ON-state characteristic impedance of the seventh field effect transistor circuit and a resistance value of the first resistor satisfies a matching condition to the characteristic impedance of a first external circuit connected to the sixth signal terminal. At the same time, sum of an ON-state characteristic impedance of the eighth field effect transistor circuit and a resistance value of the second resistor satisfies a matching condition to the characteristic impedance of a second external circuit connected to the first signal terminal. At the same time, sum of an ON-state characteristic impedance of the ninth field effect transistor circuit and a resistance value of the third resistor satisfies a matching condition to the characteristic impedance of a third external circuit connected to the fourth signal terminal. And at the same time, sum of an ON-state characteristic impedance of the tenth field effect transistor circuit and a resistance value of the fourth resistor satisfies a matching condition to the characteristic impedance of a fourth external circuit connected to the third signal terminal.
According to this configuration, the same advantageous effect as that achieved by the high frequency switch circuit of the third invention can be obtained.
The high frequency switch circuits of the second and third inventions and the communications terminals of the fifth and sixth inventions may further include a logic circuit for generating the control bias voltages to be applied to the first to tenth field effect transistor circuits. In that case, the number of control signal lines can be reduced compared with the case where the control bias voltages are directly applied to the first to tenth field effect transistor circuits.
In the high frequency switch circuits of the second and third inventions and the communications terminals of the fifth and sixth inventions, the first to tenth field effect transistor circuits may each be constructed from a single field effect transistor, or may each be constructed from a series circuit of a plurality of field effect transistors.
In the high frequency switch circuits of the second and third inventions and the communications terminals of the fifth and sixth inventions, the field effect transistors forming the field effect transistor circuits may be single-gate field effect transistors, or may be multi-gate field effect transistors.
Preferably, in the high frequency switch circuit of the third invention and the communications terminal of the sixth invention, the first to tenth field effect transistor circuits and the first to fourth resistors are formed on a semiconductor circuit.
As described above, according to the high frequency switch circuit of the present invention and the communications terminal using the same, since the high frequency switch circuit includes switches each of which is used to select whether its associated signal terminal, when unconnected to a signal path, is to be connected to the reference potential or be left open, and each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of its associated external circuit, the in-band ripple of insertion loss can be prevented and the frequency dependence of insertion loss eliminated.
Furthermore, according to the high frequency switch circuit of the present invention and the communications terminal using the same, since a field effect transistor having an ON-state characteristic impedance matched to the characteristic impedance of its associated external circuit, or a series circuit consisting of a field effect transistor and a resistor, is connected between the reference potential and a signal terminal that can become an open end, the in-band ripple of insertion loss can be prevented and the frequency dependence of insertion loss eliminated. Especially, when the series circuit consisting of a field effect transistor and a resistor is connected, since the impedance for matching can be divided between the field effect transistor and the resistor, the size of the field effect transistor can be reduced, and hence, the chip size can be reduced.